1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which wiring patterns can be simplified and in which word lines are held at a predetermined potential level so as not to float.
2. Description of Related Art
The integrated density is remarkably increased in a semiconductor memory device with the advanced fine processing technology. Specifically, in a dynamic RAM (DRAM) in which the structure of a memory cell is very simple, the increase in the integrated density is remarkable. 16-Mbit DRAM is mass-produced at present and 64-Mbit DRAM is now being forwarded as a sample.
In the 64-Mbit DRAM there is proposed as one example a divisional decoding type of semiconductor memory device in which each of word lines is divided into a plurality of sections such that memory cell can be accessed at a higher speed and a driver is provided for some of the divided sections. FIG. 1 is a block diagram showing such a divisional decoding type of semiconductor memory device.
Memory cells MCmn (m and n are integers and equal to or more than 0) are divided into a plurality blocks and a part of one block is shown in FIG. 1. The memory cells in each of the plurality of blocks is further divided into a plurality of subblocks, e.g.,there are the memory cells MC00, MC10, MC20 and MC30 in one subblock. A plurality of word line driving circuits 52a, 52b, . . . , 53a, 53b, . . . , 54a, 54b, are scatteredly provided in the block in a matrix manner. Sets of word line driving circuits in a row direction are respectively connected to sets of word line driving signal WLP0, WLP1, WLP2, . . . and word line reset signal WLP0', WLP1', WLP2', . . . , such that the word line driving circuits in one set are commonly supplied with the set of signals. A row decoder 51 decodes a part of a row address of an external address to generate the word line driving signals and word line reset signals in response to a word line precharge signal .phi.P from a circuit 58 which also generates a bit line precharge signal (not shown). Drive current supply circuits 57a to 57d decode lower two bits of the row address to generate word line selection signals RA0, RA1, RA2 and RA3 in accordance with the decoded result and supply word line driving current to sets of word line driving circuits, respectively. A pair of word line selection signals RA0 and RA2 and another pair of word line selection signals RA1 and RA3 are alternatively supplied to sets of word line driving circuits in a column direction. For instance, when the word line selection signal RA0 and the word line driving signal WLP0 are active, the circuit 57a supplies the drive current to the word line driving circuits 52a, 52c and 52e, so that the word lines WL00, WL01, WL02 and WL03 are driven. A sense amplifier (SA) 56a, 56b, 56c or 56d is provided for each of sets of subblocks of memory cells in the column direction. A pair of bit lines BL0 and BL1, BL2 and BL3, . . . is connected to each of the sense amplifiers and each memory cell is arranged at the intersection of the word line and the bit line. A dummy cell (not shown) is connected to one bit line of a pair opposing to the other bit line connected to the memory cell. For instance, with respect to a memory cell MC00 the dummy cell is constituted at the intersection of the bit line BL1 and a word line WL00 from the word line driving circuit 52a. Data is sensed from the dummy cell and the memory cell MC00 by the sense amplifier 56a and outputted onto the data lines DL0 and DL1.
All of the word line driving circuits have the same configuration and FIG. 2 is a block diagram showing the word line driving circuit 52a as a representative one of the word line driving circuits. The word line driving circuit 52a includes two self-booting types of driving circuits as shown in FIG. 2. More particularly, the word line driving circuit 52a includes two circuit parts and one includes transistors QN4, QN7 and QN8. The drain of the transistor QN4 is connected to the word line driving signal WLP0, the gate thereof is connected to a power supply line and the source thereof is connected to the gate of the transistor QN7. The drain of the transistor QN7 is connected to the word line selection signal RA0 and the source thereof is connected to the drain of the transistor QNS. The gate of the transistor QN8 is connected to the word line reset signal WLP0' and the source thereof is connected to the ground potential as a reset potential. Transistor QN4', QN7' and QN8' in the other circuit is similarly connected except that the drain of the transistor QN7' is connected to the word line selection signal RA2 in place of the signal RA0.
FIG. 3 is a block diagram schematically showing the row decoder 51 and the word line driving circuits 52a and 52c. The relation of the row decoder 51 and the other word line driving circuits is the same. With reference to FIGS. 4A to 4F, the operation of the semiconductor memory device will be described below.
In a reset mode, all of the word line precharge signal .phi.p, a row address signal, the word line selection signal RA0 and the word line WL00 is in the ground potential level as the reset potential. The word line driving signal WLP0 and the word line reset signal WLP0' are complementary and the signal WLP0' is in the power supply potential level because a P-type transistor QP2 (FIG. 3) is turned on while the signal WLP0 is in the ground potential level because of an inverter INV1. Since the signal WLP0 is in the ground potential level, the transistor QN7 is in the OFF state and because the transistor QN8 is in the ON state because of the signal WLP0', the word line WL00 is in the ground potential level.
Next, when the memory cells are to be selected in accordance with the external address, i.e., in a select mode, the circuit 58 decodes a part of an external address which designates one block to generate the word line precharge signal .phi.P which is raised to the power supply potential level as shown in FIG. 4A. After a p-type transistor QP1 goes completely to the OFF state, the row address signal is activated in the row decoder 51 by decoding a row address of the external address other than lower 2 bits as shown in FIG. 4B. If the word line driving signal WLP0 is to be selected, transistors QN1 to QN3 changes to the ON state in response to the row address signal, so that the signal WLP0' goes to the ground potential level as shown in FIG. 4C. Also, the potential of a node N1 (FIG. 2) is charged to a potential Vcc-Vth because of the output WLP0 of the inverter INV1, where Vcc is the power supply potential and Vth is a threshold voltage of the transistor QN4.
Next, when the selection signal RA0 is boosted in the drive current supply circuit 57a through decoding the lower 2 bits of the row address as shown in FIG. 4E, the self-booting of a transistor is caused so that the potential of the node N1 is raised to a further higher potential level than the boosted potential level of the selection signal RA0 to raise the potential level of the word line WL00 to the same level as that of the signal RA0, as shown in FIG. 4F.
The similar operation is performed in the word line driving circuits 52c and 52e so that the word lines WL01. WL02 and WL03 are activated.
In this manner, when one word line driving signal, e.g., the signal WLP0 is activated, the divisional word lines, e.g., the word lines WL00, WL01, WL02 and WL03 are selected based on the selection signal RA0 at a time so that the memory cells connected to the activated divisional word lines can be selected. Data of each memory cell is transferred to the sense amplifier as well as data of the corresponding dummy cell and the data is sensed there to be outputted onto the data lines.
When the access to the memory cells is completed, the precharge signal .phi.P and the row address signal are reset to the ground potential level so that the transistor QP1 changes to the ON state and the transistors QN1 to QN3 changes to the OFF state such that the signals WLP0 and WLP0' are inverted. When the word line reset signal goes to the power supply potential level and the word line driving signal goes to the ground potential level, the transistor QN7 changes to the OFF state and the transistor QN8 changes to the ON state. As the result, the word line WL00 goes to the ground potential level and is held at that level as the reset level.
As described above, in the divisional decoding type of semiconductor memory device including the word line driving circuits, the word lines are formed of polysilicon and the word line driving signal lines and the word line reset signal lines are formed of metal such as aluminium in parallel to the word lines. In this case, since the driving signal and the reset signal are complementary, when one is in the high potential level the other is in the low potential level.
Generally, the pitch between the word lines in the DRAM often takes a minimum distance which can be allowed in the manufacturing process. Therefore, the pitch between the driving signal line and the reset signal line is also not sufficient and there is a high possibility that a short circuit is formed between the driving signal line and the reset signal line because of contamination in a manufacturing process. In this case, the manufactured semiconductor memory device is fault in standby current.
In addition, with high integration in the DRAM, there are many cases that a memory cell is three-dimensionally formed for the capacitance of the memory cell as in the stacked memory cell. Therefore, a region forming the memory cells is provided to have a step for a region forming the peripheral circuit including the driving signal line and the reset signal line. On the other hand, for fine processing of the semiconductor memory device the numerical aperture of a lens in an exposing unit becomes greater and the wavelength of light becomes shorter so that the depth of focus becomes shallow. As a result of this, it is impossible to focus on the memory cell region and the peripheral region at a time. When the memory cell region is focused on, the resolution is wrong on the peripheral region. If the pitch between the driving signal line and the reset signal line is smaller, the patterns for them are not resolved so that the short circuit would be formed between them. If two processes are performed for the metal wiring of the memory cell region and the peripheral region to avoid such a case, the cost would increase.
If the number of memory cells is double in each subblock, the pitch between the driving signal line and the reset signal line can be widened. However, the driving current supply circuits such as the circuits 57a, 57b, . . . need large driving capability so that the size would becomes great. If the size is as it is, the access speed would be down.